The present invention relates to a semiconductor device functioning as a field effect transistor including a heterojunction and a method for fabricating the same.
Radio frequency (RF) semiconductor devices have heretofore been fabricated using a substrate made of a compound semiconductor like GaAs. Recently, however, technology of fabricating RF semiconductor devices using a novel mixed crystal semiconductor, which is much more compatible with a silicon process, has been researched and developed. Among other compounds, silicon germanium, which is expressed by a chemical formula Si1-xGex (where x is a mole fraction of Ge), is highly compatible with a silicon process in view of the fabrication technology applicable thereto. Thus, if Si1-xGex is used, then it is possible to take full advantage of richly cultivated silicon processing technology. In addition, SiGe and silicon (Si) together form a heterojunction therebetween. Thus, by utilizing the variability of its composition Si1-xGex (where 0<x<1) and the strain caused around the heterojunction, any device can be designed freely. Furthermore, carriers can move at a higher mobility in an SiGe layer than in an Si layer. Accordingly, a semiconductor device including an SiGe layer can operate faster with reduced noise. Paying special attention to the advantages of SiGe such as these, bipolar transistors and field effect transistors with an Si/SiGe heterojunction have been proposed, modeled and used practically.
For example, Solomon et al. of IBM Corp. proposed a heterojunction MOS transistor (HMOS transistor) including an SiGe layer as disclosed in Japanese Laid-Open Publication No. 3-3366. In this specification, the HMOS transistor of Solomon et al. will be labeled as first prior art example for convenience sake.
FIG. 13(a) is a cross-sectional view illustrating a structure of such an HMOS transistor according to the first prior art example. FIG. 13(b) is a cross-sectional view illustrating the region R50a shown in FIG. 13(a). FIG. 13(c) is a cross-sectional view illustrating movement, diffusion and segregation of Ge atoms after the HMOS transistor of the first prior art example, including a thin Si cap layer, has been annealed. And FIG. 13(d) is a cross-sectional view illustrating movement, diffusion and segregation of Ge atoms after the HMOS transistor of the first prior art example, including a thick Si cap layer, has been annealed. Only the region R50b shown in FIG. 13(b) is illustrated in FIGS. 13(c) and 13(d).
As shown in FIG. 13(a), the HMOS transistor includes: Si substrate 501; p+-type polysilicon gate electrode 516; SiO2 layer 517; intrinsic (i-) Si1-yGey layer 519 (where y is a mole fraction of Ge); i-Si cap layer 542; source contact 551 connected to a source region 553; and drain contact 552 connected to a drain region 554. In FIG. 13(a), the SiO2/Si and Si/Si1-yGey interfaces are identified by the reference numerals 535 and 536, respectively.
The HMOS transistor shown in FIGS. 13(a) through 13(c) is a p-channel MOS transistor. The source/drain regions 553 and 554 and the gate electrode 516 thereof are in similar shapes to those of an ordinary Si MOS transistor. But the p-channel is formed within Si1-yGey layer 519 to further increase the conductivity thereof. The atomic radius of Ge atoms 506 is greater than that of Si atoms. Thus, the i-Si1-yGey layer 519 receives a compressive strain because there is a lattice misfit between the i-Si1-yGey layer 519 and the Si substrate 501. Generally speaking, a phenomenon relaxing compressive strain is likely to occur during an epitaxy. Thus, it is not easy to stack the Si and SiGe layers consecutively while maintaining the crystallinity thereof. However, if the i-Si1-yGey layer 519 is deposited to a critical thickness thereof or less, then no dislocations, which ordinarily relax the strain, are brought about near the Si/Si1-yGey interface 536. As a result, these layers 519 and 542 can be stacked one upon the other in an equilibrium state with the crystallinity thereof maintained. In general, strain changes a band structure and the carrier mobility of holes. In an Si/Si1-yGey heterojunction device, however, if the Ge mole fraction y is adjusted within such a range as not causing the dislocations, then the band offset around the interface can be optimized thanks to the compressive strain and the mobility of holes can be increased. That is to say, as shown in FIG. 13(b), the holes can be confined in a heterobarrier by utilizing the offset at the valence band in the Si/Si1-yGey heterojunction device. Accordingly, the Si/Si1-yGey heterojunction device is applicable as a heterojunction PMOSFET. When a negative voltage is applied to the gate electrode 516, the polarity of the regions surrounding the Si/Si1-yGey interface 536 is inverted, thus forming a p-channel, where positive carriers (holes) are confined, along the Si/Si1-yGey interface 536. As a result, those carriers travel at a high velocity from the source region 553 toward the drain region 554. In this case, if the Si/Si1-yGey interface 536 is planar, then the p-channel is formed along the planar Si/Si1-yGey interface 536, and therefore, the carriers can move at an even higher velocity.
As can be seen, a field effect transistor using SiGe can operate faster than a field effect transistor using Si.
Ismail proposed a heterojunction CMOS transistor in 1995 IEEE IEDEM Tech. Dig. 509 (see also M. A. Armstrong, D. A. Antoniadis, A. Sadek, K. Ismail and F. Stern, 1995 IEEE IEDEM Tech. Dig. 761 and Japanese Laid-Open Publication No. 7-321222). In this specification, this HCMOS transistor will be labeled as second prior art example for convenience sake.
FIG. 14(a) is a cross-sectional view illustrating a semiconductor device according to the second prior art example. FIG. 14(b) illustrates a vertical cross section of a region including gate electrode, gate insulating film and channel in the PMOS 530 or NMOS transistor 531 shown in FIG. 14(a). On the left-hand side of FIG. 14(b), shown is a valence band corresponding to a negative gate bias voltage applied. On the right-hand side of FIG. 14(b), shown is a conduction band corresponding to a positive gate bias voltage applied. FIG. 14(c) is a cross-sectional view of the region R60b shown in FIG. 14(b) illustrating movement and segregation of Ge atoms after the HCMOS transistor of the second prior art example has been annealed. As shown in FIG. 14(a), the HCMOS transistor includes Si substrate 501, PMOSFET 530, NMOSFET 531, n-well 532 and shallow trench isolation (STI) region 534. As shown in FIG. 14(b), Si1-xGex buffer layer 523, i-Si1-xGex spacer layer 521, δ-doped layer 522, i-Si layer 520, i-Si1-yGey layer 519, i-Si layer 518, SiO2 layer 517 and polysilicon gate electrode 516 are stacked in this order. In FIG. 14(b), first, second and third interfaces are identified by the reference numerals 537, 538 and 539, respectively.
In the example illustrated in FIG. 14(a), an HCMOS device is made up of n- and p-channel field effect transistors each including the Si1-yGey layer 519. According to this prior art example, superior conductivity is attainable compared to a homojunction transistor formed on an Si substrate. In addition, since the n- and p-channel MOS transistors are formed using a common multilayer structure, the fabrication process thereof is simpler.
As shown in FIG. 14(b), strain can be relaxed by the Si1-xGex buffer layer 523, on which the i-Si1-xGex (where x=0.3) spacer layer 521 is formed. The δ-doped layer 522 for supplying carriers to the n-channel is defined within the i-Si1-xGex spacer layer 521. The i-Si layer 520 to which a tensile strain is applied, the i-Si1-yGey layer 519 of which the strain has been relaxed, and the i-Si cap layer 518 to which a tensile strain is applied, are stacked one upon the other on the i-Si1-xGex spacer layer 521. On the i-Si cap layer 518, the SiO2 layer 517 as the gate oxide film and the gate electrode 516 are formed in this order.
On the left-hand side of FIG. 14(b), shown is a valence band appearing when a negative gate bias voltage is applied to the multi-layered transistor shown in the center of FIG. 14(b) to make the transistor operate as PMOSFET. On the right-hand side of FIG. 14(b), shown is a conduction band appearing when a positive gate bias voltage is applied to the multi-layered transistor to make the transistor operate as NMOSFET. That is to say, one of the transistors can operate as PMOSFET and the other as NMOSFET by using the same multilayer structure.
To make the portion shown in the center of FIG. 14(b) operate as PMOSFET, holes are confined in the p-channel by utilizing the offset at the valence band in the first interface 537 between the i-Si1-yGey layer 519 and i-Si cap layer 518. And a negative gate bias voltage is applied to the gate electrode 516, thereby making the holes move. In this case, if the magnitude of the strain is adjusted by changing the Ge mole fraction y in the i-Si1-yGey layer 519, then the band offset in the first interface 537 is controllable. The conductivity of the holes in the i-Si1-yGey layer 519, to which the compressive strain is applied, is higher than that of the holes in the Si layer. Thus, excellent PMOS performance is attainable.
To make the portion shown in the center of FIG. 14(b) operate as NMOSFET, electrons are confined in the n-channel by utilizing the offset at the conduction band in the third interface 539 between the i-Si layer 520 and i-Si1-xGex spacer layer 521. And a positive gate bias voltage is applied to the gate electrode 516, thereby making the electrons move. Unlike the PMOSFET, the n-channel is formed within the Si layer 520. However, the i-Si layer 520 is receiving a tensile strain because there is a lattice misfit between the i-Si layer 520 and i-Si1-xGex spacer layer 521. Accordingly, the band degeneracy of the electrons has been eliminated and the conductivity of the electrons is higher than that of electrons located within a normal channel in the Si layer. In this case, if the magnitude of the strain is adjusted in the same way as the PMOSFET, then the band offset is also controllable.
As can be seen, in the semiconductor device according to the second prior art example where the Si/SiGe heterojunctions are formed, the same multilayer structure shown in the center of FIG. 14(b) can be selectively used as NMOSFET or PMOSFET by changing the direction of the gate bias voltage. Accordingly, an HCMOS device with excellent conductivity can be obtained through relatively simple process steps if a single multilayer structure is separated and isolated via the STI to define separate source/drain regions and gate electrode.
However, the devices according to the first and second prior art examples have the following drawbacks.
In the field effect transistors such as the MOSFET according to the first prior art example, carriers travel along the inversion region around the Si/Si1-yGey interface 536. Thus, the interface states greatly affect the mobility of the carriers, and the operating speed of the device. That is to say, to make the device operate at high speeds, the structure of the Si/Si1-yGey interface 536 should not be out of order, i.e., the interface thereof should be definitely defined and planar without any fluctuations or unevenness.
However, it is difficult for the device using the Si/Si1-yGey heterojunction to maintain the definitely defined, planar interface because of the following reasons.
For example, when the i-Si1-yGey layer 519 and i-Si cap layer 542 are stacked consecutively as shown in FIG. 13(b), then interdiffusion is caused between Si atoms (not shown) in the i-Si cap layer 542 and Ge atoms 506 in the i-Si1-yGey layer 519. As a result, the structure of the Si/Si1-yGey interface 536 becomes out of order and the boundary between the i-Si1-yGey layer 519 and i-Si cap layer 542 cannot be located definitely anymore. In FIG. 13(b), the i-Si1-yGey layer 519 and i-Si cap layer 542 are illustrated as being clearly divided layers for the illustrative purposes only. Actually, though, the boundary between these layers 519 and 542, i.e., the interface 536, is not so definite as the illustrated one.
In a fabrication process of a semiconductor device such as a field effect transistor, just after dopants have been introduced by ion implantation, for example, to define p- and n-type doped regions, those dopants are not located at crystal lattice sites. Thus, to make these dopants act as donors or acceptors, annealing is conducted at an elevated temperature, thereby activating the dopants. In this case, annealing is carried out at a temperature as high as about 900° C. Thus, the Ge atoms 506 in the i-Si1-yGey layer 519 move and diffuse particularly actively.
FIGS. 13(c) and 13(d) are cross-sectional views illustrating post-annealing states of the region R50b shown in FIG. 13(b) where the thicknesses of the i-Si cap layer 542 are relatively small and large, respectively. As a result of annealing, the Ge atoms 506 move and diffuse to cause segregation or lattice defects and the definiteness and planarity of the Si/Si1-yGey interface 536 are lost as disclosed by F. K. LeGoues, S. S. Iyer, K. N. Tu and S. L. Delage in Mat. Res. Soc. Symp. Proc., Vol. 103, 185 (1988). As also described in this document, the movement, diffusion and segregation of the Ge atoms are particularly noticeable in an SiGe layer to which some strain is applied.
According to the first and second prior art examples, the SiO2 layer 517 is formed as the gate oxide film by thermal oxidation. However, during the thermal oxidation, the Ge atoms are segregated at the Si/SiO2 interface 535 and increase the oxidation rate as disclosed by G. L. Patton, S. S. Iyer, S. L. Delage, E. Ganin and R. C. Mcintosh in Mat. Res. Soc. Symp. Proc., Vol. 102, 295 (1988). Such a phenomenon is believed to cause various adverse effects. For example, the interface level of the Si/SiO2 interface 535 rises, thus adversely affecting the mobility of carriers moving in the p-channel. The concentration distribution of Ge atoms might deviate from a desired one. And since the oxidation rate increases, it might become difficult to form a thin gate oxide film.
Thus, if the thickness of the i-Si cap layer 542 is set larger than the diffusion length of the Ge atoms as shown in FIG. 13(d), it might be possible to prevent the carrier mobility from being adversely affected by the structural disorder of the Si/Si1-yGey interface 536. In such a case, however, a potential difference is also applied to the i-Si cap layer 542. Accordingly, the driving power of the transistor might possibly decrease. Also, since a parasitic channel is formed near the Si/SiO2 interface 535 as shown in FIG. 13(d), the carriers might deviate from the intended path and the mobility thereof might decrease as a result. In addition, the structural disorder of the Si/Si1-yGey interface 536 and the lattice defects such as dislocations resulting from the annealing process are still left as they are.
Some countermeasures have been taken to solve such problems. For example, the annealing temperature could be lowered to a certain degree if the i-Si1-yGey layer 519 and i-Si cap layer 542 are grown epitaxially after the dopant ions have been implanted into the Si substrate 501 to define source/drain regions and then activated through annealing. In such a case, however, the ion-implanted regions and the gate electrode 516 cannot be self-aligned with each other, thus increasing the number of process steps. In addition, the dopant profile and gate alignment accuracy deteriorates due to the mask-to-mask placement error involved with a photolithographic process.
The drawbacks of the first prior art example have been specified above. It is clear that the same statement is true of the second prior art example, because structural disorder is also brought about in the first and second Si/Si1-yGey interfaces 537, 538 and in the third Si/Si1-xGex interface 539.